Semiconductor device and method for manufacturing the semiconductor device

ABSTRACT

A method is used for manufacturing a semiconductor device including a circuit-fabricated side on which an encapsulation layer is formed. The method includes the following steps. A semiconductor wafer is placed on the suction surface of a suction stage, the suction surface having a diameter in the range of 99 to 100.5% of a diameter of the semiconductor wafer. The semiconductor wafer is held on the suction surface of the suction stage by suction. A back surface of the semiconductor wafer is ground. The back surface of the semiconductor wafer is ground such that a surface roughness of the ground back surface is not greater than 5 nm. The encapsulation layer has a flexural modulus not smaller than 12 Gpa and not larger than 18 Gpa.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method formanufacturing the semiconductor device, and more particularly to amethod for manufacturing small semiconductor devices such as a waferlevel chip size package (WCSP) in which a plurality of circuit elementsare formed on a semiconductor wafer and then the semiconductor wafer issliced into individual dice.

2. Description of the Related Art

Recently, there have been strong demands in the field of electronicequipment towards miniaturized and thinner packages. The thickness ofpassive components such as capacitors and resistors mounted On a circuitboard has been reduced to about 200 μm. This trend has also placeddemands on active components such as memories and CPUs having as small athickness as the capacitors and resistors.

WCSP type semiconductor devices are generally of the construction inwhich circuits are fabricated on one side of a semiconductor substrate(e.g., Si) and are sealed with a sealing layer of resin. Because theencapsulation layer and the semiconductor substrate have differentphysical values (primarily thermal expansion coefficient), when they arelaminated, the semiconductor substrate tends to extend outward. Oneproblem with grinding a semiconductor wafer at its back side surface isthat a thinner wafer causes the semiconductor substrate to tend toextend further outward.

A thin semiconductor wafer may be manufactured by grinding the backsurface of the semiconductor wafer while maintaining the semiconductorflat in the following way. A protection tape is attached to the circuitside of the semiconductor wafer. Then, the semiconductor wafer ismounted on a suction stage with the protection tape between thesemiconductor wafer and the suction stage. After grinding, thesemiconductor wafer is transferred to the next process with theprotection tape attached to the semiconductor wafer. Then, a die bondingfilm is attached to the side of the wafer opposite to the protectiontape, and then the protection tape is removed from the semiconductorwafer. In this manner, warpage of a semiconductor wafer is prevented.

Alternatively, a thin semiconductor wafer may be manufactured bygrinding the back surface of the semiconductor wafer while maintainingthe semiconductor flat in the following way. After coarse grinding, theground wafer is sucked to a suction pad that is as large as the outergeometry of the wafer, and then the semiconductor wafer is released fromthe suction stage. Subsequently, the semiconductor wafer is transferredto a fine grinding apparatus. This allows the wafer to be maintainedflat during the coarse grinding and fine grinding. In this manner,warpage of a semiconductor wafer after fine grinding may be minimized.

The aforementioned techniques are used for grinding the back surface ofa semiconductor device while also maintaining the semiconductor waferflat, enabling manufacturing of a thin semiconductor device. For alaminated structure of a semiconductor wafer and an encapsulation layerof resin, warpage of the semiconductor wafer is due to the difference inthermal expansion coefficient between the wafer and the encapsulationlayer. Thus, once the semiconductor wafer is released from the devicefor maintaining the wafer flat, the semiconductor wafer tends to bewarped excessively.

Careful investigation of various conditions for grinding the backsurface of a semiconductor wafer revealed the following facts.

(1) Warpage of a semiconductor wafer is enhanced if chipping (e.g.,larger than 100 μm) occurs at many locations on the circumference of thewafer. Poor surface roughness of the wafer due to the chipping impairsthe resistance of the wafer to warpage, promoting further warpage.

(2) Warpage of a semiconductor wafer depends on the surface roughness ofa wafer after grinding. High surface roughness impairs the resistance ofthe back surface of wafer to warpage, promoting warpage of the wafer.

(3) Warpage of a semiconductor wafer depends on the flexural modulus ofan encapsulation layer at room temperature. There exists an optimumvalue of flexural modulus regardless of the thickness of a semiconductorsubstrate.

SUMMARY OF THE INVENTION

An object of the invention is to provide a method for minimizing thewarpage of a semiconductor wafer during a grinding stage of themanufacturing process of a semiconductor device.

Another object of the invention is to provide a semiconductor devicehaving minimum warpage.

A method is used for manufacturing a semiconductor device including acircuit-fabricated side on which an encapsulation layer is formed.

The method includes the following steps:

placing a semiconductor wafer on a suction surface of a suction stage,the suction surface having a diameter in the range of 99 to 100.5% of adiameter of the semiconductor wafer;

holding the semiconductor wafer on the suction surface of the suctionstage by suction; and

grinding a back surface of the semiconductor wafer.

The grinding is performed such that a surface roughness of the groundback surface is not greater than 5 nm.

The method further includes forming the encapsulation layer having aflexural modulus not smaller than 12 Gpa and not larger than 18 Gpa.

Further scope of applicability of the present invention will becomeapparent from the detailed description given hereinafter. However, itshould be understood that the detailed description and specificexamples, while indicating preferred embodiments of the invention, aregiven by way of illustration only, since various changes andmodifications within the spirit and scope of the invention will becomeapparent to those skilled in the art from this detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from thedetailed description given hereinbelow and the accompanying drawingswhich are given by way of illustration only, and thus are not limitingthe present invention, and wherein:

FIG. 1 is a fragmentary cross-sectional side view of a semiconductorwafer of an embodiment according to the present invention, illustratinga method for manufacturing the semiconductor wafer;

FIG. 2 illustrates the method for manufacturing the semiconductor waferof the embodiment;

FIG. 3 is a fragmentary cross-sectional side view illustrating a backsurface grinding apparatus used at Process #8;

FIG. 4 illustrates the relation between the suction surface and thewarpage of a semiconductor wafer;

FIG. 5 illustrates the relationship between the surface roughness andthe warpage of the semiconductor wafer;

FIG. 6 illustrates the relationship between the warpage of thesemiconductor wafer and the flexural modulus of a resin material for anencapsulation layer; and

FIG. 7 illustrates the relationship between the flexural modulus of theresin material and the flexural strength of a semiconductor device.

DETAILED DESCRIPTION OF THE INVENTION

An embodiment of a method of manufacturing a semiconductor waferaccording to the present invention will be described with reference tothe accompanying drawings.

Embodiment

FIG. 1 is a fragmentary cross-sectional side view of a semiconductorwafer 1 illustrating a method for manufacturing the semiconductor wafer.FIG. 2 is another cross-sectional side view of the semiconductor waferillustrating the method. FIG. 3 is a fragmentary cross-sectional viewillustrating a back surface grinding apparatus used at Process #8, whichwill be described later.

FIG. 1 is a side view of the semiconductor wafer with a partialcross-sectional view, and illustrates the vicinity of electrode padsformed on a semiconductor wafer and post electrodes connected to theelectrode pads via rerouting traces. Referring to FIGS. 1 and 2, thesemiconductor wafer 1 is an 8-in disc-shaped semiconductor wafer onwhich a plurality of WCPS type semiconductor devices are formedsimultaneously.

A semiconductor substrate 2 is bulk silicon, which is a part of thesemiconductor wafer 1. The semiconductor substrate 2 has a thickness inthe range of 0.5 to 1 mm. A plurality of circuit elements are formed onthe front surface (i.e., circuit surface 3) of the semiconductorsubstrate 2, being interconnected by wiring. An insulating layer 4 isformed of an insulating material such as silicone dioxide (SiO₂), and isformed on the circuit surface 3. Contact holes are formed over therespective circuit elements on the semiconductor substrate 2.

Electrode pads 5 (only one is shown in FIG. 1) are formed by etching anelectrically conductive layer of aluminum (Al) or titanium (Ti) formedon the insulating layer 4. The electrode pad 5 is electrically connectedto a part of a circuit element via a conductor buried in the contacthole formed in the insulating layer 4. A surface protection film 6covers both the electrode pad 5 and the insulating layer 4 formed of aninsulating material such as silicon nitride (Si₃N₄).

An interlayer dielectric film 7 is formed of an insulating material suchas polyimide, and is formed on the surface protection film 6. Theinterlayer dielectric film 7 is etched away at a portion over theelectrode pad 5 to form a through-hole 8 to the electrode pad 5. A thinmetal layer 9 takes the form of a multi-layer of electrically conductivematerials such as titanium (Ti), titanium nitride (TiN), copper (Cu) andthe like. The thin metal layer 9 covers the entire front surface of thesemiconductor wafer 1. The thin metal layer 9 covers the interlayerdielectric film 7, the inner surface of the through-hole 8, and theelectrode pad 5.

A rerouting trace 10 is a rerouting element of, for example, copperformed on the electrode pad 5, and extends to an electrode region 12 inwhich a post electrode 11 is formed. The rerouting trace 10 is connectedto the electrode pad 5 via an underlying metal layer 9, thereby makingelectrical connection between the post electrode 11 and the electrodepad 5.

The post electrode 11 is a cylindrical projection formed of the samematerial as the rerouting trace 10, and has a height of about 100 μm. Abump electrode 13 is a hemispherical electrode of, for example, solder.The bump electrode 13 is formed on a top end surface of the postelectrode 11, and serve as a terminal for connecting the semiconductordevice to an external circuit. The post electrode 11 is connected to thewiring terminal on a circuit board on which the semiconductor device ismounted. The circuit elements on the semiconductor substrate 2 areconnected to extend through the electrode pad 5, metal layer 9,rerouting trace 10, post electrode 11, and bump electrode 13.

An encapsulation layer 15 is an insulating layer having a thickness ofabout 100 μm. The encapsulation layer 15 is formed of a sealing resin(e.g., thermosetting epoxy resin) deposited on the front surface of thesemiconductor wafer 1 and thermally cured. The encapsulation layer 15protects the semiconductor device 30 from humidity in the environment. Aprotection tape 17 has flexibility such that the protection tape 17 hasa side surface that accommodates the ridges and follows of the bumpelectrodes 13 and that may be cured when it is exposed to ultravioletlight. The protection tape 17 is a single-sided tape having a stickylayer on its one side. The sticky layer is softened when it isirradiated with ultraviolet light. During a grinding process of the backsurface of the semiconductor wafer 1, the protection tape 17 protectsthe front surface of the semiconductor wafer 1 on which circuits arefabricated.

A resist mask 18 is formed by means of photolithography in which aresist is applied to the front surface of the semiconductor wafer 1, isthen exposed to light, and is finally developed into a mask.

FIG. 3 illustrates a back surface grinding apparatus 20. When the backsurface 1 a of the semiconductor ware 1 is ground, the protection tape17 attached to the semiconductor wafer 1 is directly sucked onto asuction stage 21 and the suction stage 21 rotates with the semiconductorwafer 1 mounted there on. The suction stage 21 has a negative pressurechamber 22 formed in its central portion, a negative pressure beingsupplied to the pressure chamber 22 to hold the semiconductor ware 1 bysuction.

A suction plate 23 is formed of a porous ceramic material in the shapeof a disc that has a suction surface 23 a and almost the same diameteras the semiconductor wafer 1. The suction plate 23 is mounted to anupper opening of the negative pressure chamber 22 such that the uppersurface of the suction plate 23 is flush with the upper surface of thesuction stage 21. A grinder 25 includes a grindstone 26 in which hardabrasive grains such as diamond and a non-organic filler are compressedinto a ring-shape with the aid of a resin material and/or a metal andare then sintered. The grinder 25 rotates at high speed to grind theback surface 1 a of the semiconductor wafer 1. The grinder 25 ispositioned relative to the semiconductor wafer 1 such that the grindingsurface 26 a of the grindstone 26 extends in a direction that passesthrough the substantially the central portion of the semiconductor wafer1.

For an 8-in semiconductor wafer, the suction surface 23 a of the backsurface grinding apparatus 20 has a diameter of about 200 mm as opposedto a conventional back surface grinding apparatus (e.g., Model DFG-841available from Disco) having a suction surface with a diameter of 186mm. Thus, the suction surface 23 a is capable of sucking the entiresurface of the semiconductor wafer 1. The method of manufacturing asemiconductor device of the embodiment will be described with referenceto FIGS. 1 and 2.

Process #1: A plurality of circuit elements, not shown, are formed onthe circuit surface 3 of the semiconductor substrate 2. Contact holes,not shown, are formed in the insulating layer 4 at locations over therespective circuit elements by chemical vapor deposition (CVD). Anelectrically conductive layer is formed on the insulating layer 4 bysputtering. Then, the insulating layer 4 is selectively etched away toform electrode pads 5 having a predetermined shape. The electrode pads 5make electrical connection between the circuit elements.

After forming the electrode pads 5, a surface protection film 6 isformed of a silicon nitride by CVD, covering the electrode pads 5 andinsulating layer 4. The surface protection film 6 is selectively etchedso that the electrode pads 5 are exposed. Then, an interlayer dielectricfilm 7 is formed on the surface protection film 6 and the electrode pads5, and then portions of the interlayer dielectric film 7 over theelectrode pads 5 are etched away, thereby forming through-holes 8 in theinterlayer dielectric film 7. Thus, the through-holes 8 extend as deepas the electrode pad 5.

Process #2: A base metal layer 9 is formed on the front surface of thesemiconductor wafer 1 by sputtering. The base metal layer 9 includes aplurality of layers, and covers the interlayer dielectric film 7 and theelectrode pad 5. A resist mask 18 is formed by means ofphotolithography, and covers an area except for the area of the basemetal layer 9 from the electrode pad 5 to the electrode region 12. Then,a conductive material is electrocoated on the base metal layer 9 byelectroplating, thereby forming the rerouting trace 10 that extends fromthe electrode pad 5 to the electrode region 12.

Process #3: The resist mask 18 formed in Process #2 is removed by aresist remover, and another resist mask 18 is formed by means ofphotolithography. The resist mask 18 covers the front surface of thesemiconductor wafer 1 except for the electrode region 12 over thererouting trace 10. Then, a conductive material is electrocoated on thererouting trace 10 by electroplating, thereby forming the post electrode11.

Process #4: The resist mask 18 formed in the Process 3 is removed byusing a resist remover. Then, the base metal layer 9 is removed by wetetching except for an area of the rerouting trace 10 and the postelectrode 11.

Process #5: The semiconductor wafer 1 is placed in an encapsulationmold, not shown, and a resin is introduced into a space above the frontsurface of the semiconductor wafer 1 in the encapsulation mold. Theencapsulation mold presses the peripheral portion of the front surfaceof the semiconductor wafer 1 to prevent leakage of the resin and/orspreading around the back surface 1 a of the semiconductor wafer 1. As aresult, there will be a peripheral area 1 b of the semiconductor wafer 1where no encapsulation layer 15 is formed, creating a step. Theperipheral portion 1 b is about 2 mm wide which represents about 4% ofthe diameter of the semiconductor wafer 1.

Process #6: The semiconductor wafer 1 is taken out of the encapsulationmold. The front surface of the encapsulation layer 15 is ground so thattop ends 11 a of the post electrodes 11 are exposed to the front surfaceof the encapsulation layer 15 and are flush with the front surface ofthe encapsulation layer 15. The resulting encapsulation layer 15 has athickness of about 100 μm.

Process #7: Solder is printed on the top end 11 a and then the solder ismelted, thereby forming a hemispherical bump electrode 13 that projectsupwardly from the top end 11 a.

Process #8: The protection tape 17 is attached to the semiconductorwafer 1 such that the adhesive-coated side of the protection tape 17contacts the front surface of the semiconductor wafer 1 on which thebump electrodes 13 are formed. Then, the protection tape 17 is cut tosubstantially the same diameter as the semiconductor wafer 1. Thesemiconductor wafer 1 is then flipped over, and is placed on the suctionstage 21 of the back surface grinding apparatus 20 with the protectiontape 17 abutting the suction surface 23 a. A negative pressure issupplied from a negative pressure source such as a vacuum pump to thenegative pressure chamber 22 such that the entire surface of thesemiconductor wafer 1 is sucked to the suction surface 23 a.

The suction stage 21 and grinder 25 are rotated to grind the backsurface 1 a of the semiconductor substrate 2 until the semiconductorsubstrate 2 has a thickness in the range of 50-300 μm (e.g., 190 cm inthe embodiment).

Process #9: After grinding the back surface 1 a, the protection tape 17on the semiconductor wafer 1 is irradiated with ultraviolet light sothat the adhesive layer cures. Then, the protection tape 17 is peeledoff from the semiconductor wafer 1. Then, a resilient tape 28 isattached to the front surface of the semiconductor wafer 1. Then, thesemiconductor wafer 1 is cut along lines known as “street indices”provided on the front surface of the semiconductor wafer 1 by using ablade 29, thereby slicing the semiconductor wafer 1 into individualdice.

Process 10: The individual dice, i.e., WCSP type semiconductor devices30 are each transferred onto a chip tray by means of, for example, arobot arm. In this manner, miniaturized WCSP type semiconductor devices30 having a thickness not larger than 0.5 mm are manufactured.

During the aforementioned manufacturing process, in order to minimizewarpage of the semiconductor wafer 1, it is vitally important to preventchipping at a large number of locations of the peripheral portion 1 b ofthe semiconductor substrate 2. The suction stage 21 usually has a smallsuction surface, and the stepped portion 1 b surrounding theencapsulation layer 15 has low rigidity. Chipping at the peripheralportion 1 b appears to occur due to the fact that the semiconductorsubstrate 2 flutters or vibrates at its stepped portion 1 b during thegrinding operation at Process #8.

FIG. 4 illustrates the relation between the suction surface of thesuction stage and the warpage of the semiconductor wafer 1. FIG. 4 plotsthe ratio of diameter of the suction surface 23 a to that of thesemiconductor wafer 1 (i.e., diameter ratio) as the abscissa, and thewarpage of the semiconductor wafer 1 as the ordinate.

The semiconductor wafer 1 under test has the following dimensions.

The semiconductor substrate 2 has a thickness of 190 μm. Theencapsulation layer 15 has a thickness of 90 μm. The semiconductor wafer1 has a diameter of 200 mm. Referring to FIG. 4, the warpage of thesemiconductor wafer begins to decrease when the diameter ratio exceeds97%. Warpage of the semiconductor wafer 1 remains low for diameterratios in the range of 99-100.5%, and increases rapidly for diameterslarger than 100.5%.

In other words, the diameter of the suction surface 23 a is preferablynot smaller than 99% and not more than 100.5%. For diameter ratios notlarger than 99%, the suction surface is too small in area, causing theperipheral portion 1 b of the semiconductor wafer 1 to flutter. Fordiameter ratios larger than 100.5%, areas of the suction surface 1 a notcovered by the semiconductor wafer 1 increase, and therefore a largefraction of the negative pressure escapes. This causes the peripheralportion 1 b of the semiconductor wafer 1 to flutter.

When the front surface of the semiconductor wafer 1 is sucked to thesuction surface 23 a, the peripheral portion 1 b does not flutterprovided that the suction surface 23 a has a diameter in the range of 99to 100.5% of that of the semiconductor wafer 1. This prevents chippingfrom occurring at the peripheral portion 1 b of the semiconductor wafer1 that would otherwise cause a significant decrease in the force forholding the semiconductor wafer 1 against warpage. Thus, thesemiconductor wafer 1 will not crack due to chipping at the peripheralportion 1 b.

In order to sufficiently minimize warpage of the semiconductor wafer 1,it is important that the surface roughness of the back surface 1 a ofthe semiconductor wafer 1 be improved. FIG. 5 illustrates therelationship between the surface roughness and the warpage of the wafer.FIG. 5 plots the surface roughness Ra as the abscissa and the warpage ofthe wafer as the ordinate.

The semiconductor wafer 1 under test has the following dimensions.

The semiconductor substrate 2 has a thickness of 190 μm. Theencapsulation layer 15 has a thickness of 90 μm. The diameter of thesemiconductor wafer 1 has a diameter of 200 mm.

Points E, F, and G denote grinding operation at Process #8 performedwith the grindstones 26 of #8000, #5000, and #2000, respectively. Theresults in FIG. 5 reveal that the warpage of the semiconductor wafer 1decreases with improvement of the surface roughness of the semiconductorwafer 1.

For reliable chucking of the semiconductor wafer 1 during transportationof the semiconductor wafer 1, and stability of the semiconductor wafer 1when the semiconductor wafer 1 is accommodated in a magazine, thesurface roughness of the back surface 1 a of the semiconductor wafer 1is preferably not more than Ra=5 nm. If the semiconductor wafer 1 iswarped more than Ra=5 nm, the chucking performance of the semiconductorwafer 1 during transportation of the semiconductor wafer 1 decreases sothat the semiconductor wafer 1 may drop to be damaged or the posture ofthe semiconductor wafer 1 becomes unstable when the semiconductor wafer1 is accommodated in the magazine. This tends to cause crack in thesemiconductor wafer 1.

The minimum surface roughness should preferably be not less than Ra=1nm. A surface having a surface roughness less than 1 nm does not serveas an effective gettering site that collects unnecessary metal impurityin the active region in which circuit elements are formed, and thereforethe electrical properties of semiconductor devices 30 deteriorate. Thus,controlling the surface roughness of the ground back surface 1 a of thesemiconductor wafer 1 to be not larger than 5 nm will decrease theroughness of the back surface 1 a, improving the ability of thesemiconductor wafer 1 to resist against warpage.

The flexural modulus of the encapsulation layer 15 in intimate contactwith the semiconductor wafer 1 is another factor that determines thewarpage of the semiconductor wafer 1. FIG. 6 illustrates therelationship between the warpage of the semiconductor wafer 1 and theflexural modulus of the resin material of the encapsulation layer 15.FIG. 6 plates the flexural modulus of the encapsulation layer 15 as theabscissa and the warpage of the semiconductor wafer 1 as the ordinate.

The semiconductor wafer 1 under test has the following dimensions.

The semiconductor substrate 2 has a thickness of 90 μm. Theencapsulation layer 15 has a thickness of 90 μm. The diameter of thesemiconductor wafer 1 has a diameter of 200 mm. The plot in FIG. 6reveals that the warpage of the semiconductor wafer 1 is a minimum whenthe flexural modulus is 14 Gpa. The warpage increases for the values offlexural modulus larger than 14 Gpa and smaller than 14 Gpa.

The flexural modulus of the encapsulation layer 15 directly affects theflexural strength of the semiconductor device 30, and therefore theflexural strength is a crucial consideration. FIG. 7 illustrates therelation between the flexural modulus of the resin material for theencapsulation layer 15 and the flexural strength of the semiconductordevice 30. FIG. 7 plots the flexural modulus of the encapsulation layer15 at room temperature as the abscissa and the bending fracture stressof the semiconductor device 30 as the ordinate.

Referring to FIG. 7, the flexural strength is a maximum when theflexural modulus of the resin material for the encapsulation layer 15 is18 Gpa, and decreases for values of flexural modulus of higher than 18Gpa and lower than 18 Gpa. In order to minimize the warpage of thesemiconductor wafer 1, the flexural modulus of the encapsulation layeris preferably not smaller than 12 Gpa and not greater than 18 Gpa.Flexural modulus less than 12 Gpa offers warpage of the semiconductor ina reasonable range but the flexural strength of the semiconductor device30 is too low. Flexural modulus greater than 18 Gpa offers the flexuralstrength of the semiconductor device 30 in a reasonable range butwarpage of the semiconductor is too large.

The sealing resin having a flexural modulus in the aforementioned rangemay be made by adjusting the amount of filler that is mixed in theencapsulation resin material. For example, the encapsulation layer 15having a flexural modulus in the aforementioned range may be formed of athermosetting epoxy resin that contains silica filler by 80 to 85%.

The aforementioned semiconductor device 30 has substantially the samethickness as neighboring passive components mounted on a circuit board,so that when circuit boards are stacked one over the other, the overallthickness of the stacked structure may be small enough, implementing athin structure of electronic equipment. Although the semiconductorsubstrate of the semiconductor wafer has been described as a bulksubstrate of silicon, the semiconductor wafer may also include those inthe form of silicon on insulator (SOI) and silicon on sapphire (SOS).

1. A method for manufacturing a semiconductor device including acircuit-fabricated side on which an encapsulation layer is formed, themethod comprising: placing a disc-shaped semiconductor wafer on asuction surface of a suction stage, the sucking area having a diameterin the range of 99 to 100.5% of a diameter of the semiconductor wafer;holding the semiconductor wafer on the suction surface of the suctionstage by suction; and grinding a back surface of the semiconductorwafer.
 2. The method for manufacturing a semiconductor device accordingto claim 1, wherein grinding is performed such that a surface roughnessof the back surface is not greater than 5 nm.
 3. The method formanufacturing a semiconductor device according to claim 1, furthercomprising forming the encapsulation layer having a flexural modulus notsmaller than 12 Gpa and not larger than 18 Gpa at room temperature.